It was in 1974, precisely 50 years ago, that Hosokawa et al. [1] performed their experiment giving rise to the Reactive Ion Etching (RIE) process, and that Suntola [2] in Finland proposed a deposition process that was to become the ALD (atomic layer deposition) process. These two processes are now irreplaceable in microelectronics chip manufacturing.
In this tutorial, we’ll try to show how etching and deposition processes have innovated over the last 50 years, and how they now combine to open the door to new concepts that facilitate integration, such as selective deposition (Area Selective Deposition – ASD).
[1] N. Hosakawa, R. Matsuzaki and T. Asamaki, “RF sputter-etching by fluoro-chloro-hydrocarbon gases” Proc. 6th Int. Vacuum Congr. 1974, Jpn J. Appl. Phys. Suppl. 2, Pt. 1, 1974.
[2] R.L. Puurunen, Chem. Vap. Deposition 2014, 20, 332–344

Christophe Vallée received his Ph.D. degree in physics from the University of Nantes (France) in 1999. His research activity focuses on plasma and atomic scale processes. He is currently professor at CNSE, University at Albany (USA). Until September 2020 he was a professor at Grenoble Alpes University (France) and a visiting professor at Tsukuba University (2016-2020). He has authored and co-authored > 100 peer-reviewed publications.

High-k compounds play an important role in semiconductor devices such as insulating film for the gate electrodes in MOSFETs. The insulating film for the gate electrode must have sufficient thickness to prevent current leakage, which degrades device performance. On the other hand, a thicker film is less susceptible to gate voltage. Semiconductor devices are required to have both high susceptibility and current leakage suppression. To satisfy these requirements, the film must have a sufficiently high dielectric constant.
ZrO₂ and HfO₂ are promising candidates for high-k dielectrics, whose dielectric constants are higher than that of SiO₂ currently used in most devices. ZrO₂ and HfO₂ are known to exhibit crystal polymorphism. The monoclinic structures are stable at room temperature and have lower dielectric constants than the tetragonal structures. Stabilization of the tetragonal structure is expected to improve device performance. In this work, we analyze the impurity doping effects on the structural stability of the tetragonal phase of ZrO₂ and HfO₂, considering the configuration of impurities to find possible candidates of dopant atoms by using first – principles calculations and informatics methods.

Prof. Yasuteru Shigeta, a Theoretical Chemist, graduated from Department of Chemistry, Osaka University and obtained PhD in 2000. He pursued his postdoctoral research at Osaka University, Kansas State University, and the University of Tokyo. He worked at the University of Tokyo during 2004 – 2007(Assistant professor), University of Tsukuba during 2007 – 2008 (Lecturer), University of Hyogo during 2008 – 2010 (Associate professor), Osaka University during 2010 – 2014 (Associate professor), and joined University of Tsukuba as a full professor since 2014. He has published more than 300 scientific papers and received the PCCP award of Royal Society of Chemistry (UK) in 2007, Young – chemists award of the Chemical Society of Japan in 2009, the Young – scientists award of MEXT Japan in 2010, the Young
– scientists award of Japan Society for Molecular Science in 2012, the QSCP Promising Scientist Prize of CMOA in 2017, and International Science Award of Japan Society for Molecular Science in 2023.

Since 1985, I have been responsible for the research, development, and mass production of semiconductor lithography, particularly exposure tool, at Toshiba. The history of semiconductor lithography has been driven primarily by the demand for device pattern shrinking. Over the past few decades, this pursuit has led to significant improvements in performance and reductions in cost. However, as device pattern shrinking approaches theoretical limits, we are exploring new methods.
In this presentation, I will first introduce the history of semiconductor lithography technology and discuss how we have overcome many challenges that were once deemed impossible. Additionally, I will address future prospects.
Recently, advancements have begun in areas where lithography and data science converge, such as Design Technology Co-Optimization (DTCO) and Design Manufacturing Co-Optimization (DMCO).
I will present examples of next-generation process developments, highlighting the potential for pioneering new fields to optimize processes and reduce defect rates in these areas. This presentation aims to provide insights into the evolution of semiconductor lithography and the innovative solutions being developed to address the challenges of the future.

I am currently affiliated with KIOXIA Corporation’s Research Strategy Planning Office at the Frontier Technology R&D Institute. Joining Toshiba’s ULSI Research Laboratory in 1985, I have been involved in the development of semiconductor lithography technology, particularly pioneering new alignment techniques for semiconductor exposure tools.
During the first decade, I contributed to the design and development of in-house exposure tools at Toshiba.
Subsequently, I led the development of semiconductor exposure tools in collaboration with exposure tool manufacturers, focusing on advancing technologies like KrF excimer laser, Scanner, Arf high NA Immersion, and nanoimprint exposure tools for mass production.
Currently, I am engaged in talent development at our company, integrating data science with processes.
In 1994, I earned a Ph.D. in Engineering for research and development of “SMART (separated mark through the lens) alignment” in semiconductor KrF exposure tool.

Professor Kuroda received his PhD in Electrical Engineering from the University of Tokyo in 1982, and joined Toshiba Corporation the same year. He was a visiting researcher at the University of California, Berkeley, from 1988 to 1990. He left Toshiba to join Keio University in 2000, and became a full professor in 2002. He was the Mackay Professor at the University of California, Berkeley, in 2007. He has been a professor at The University of Tokyo since 2019. He was the director of System Design Lab (d.lab) . He is the chairperson of RaaS. In 2024 he was appointed to University Professor, Office of University Professor, The University of Tokyo and Chancellor, Prefectural University of Kumamoto.
Dr. Kuroda has presented 40 papers at ISSCC, 29 at VLSI Symposia, 19 at CICC, and 18 at A-SSCC. In addition, he has authored 30 books and holds more than 200 patents. He is a member of the IEEE SSCS Administrative Committee, an IEEE Distinguished Lecturer, an IEEE/SSCS Region 10 Representative, an IEEE Fellow, and an IEICE Fellow.