I will present recent trends in advanced packaging technologies (2D, 2.5D, 3.5D, CPO) and explain our research results (thermal management, hybrid bonding, etc.)

I received a Ph.D. in Engineering from Tohoku University
At Bosch, I was involved in the development of physical sensors using semiconductor technology. I then moved to Waseda University, where I conducted research and development on core semiconductor technologies (surface treatment, bonding) and physical sensors. Currently, at National Cheng Kung University, I am engaged in research and development on heterogeneous integration, focusing primarily on semiconductor back-end processes. I am collaborating on joint research projects with nine Japanese companies, three Taiwanese companies, and four universities.

The rapid evolution of AI demands a paradigm shift in semiconductor performance, specifically in compute density and memory bandwidth. To meet these requirements, the industry is aggressively scaling logic and memory while pivoting toward heterogeneous integration. These architectural shifts impose a new frontier of technical requirements on lithography tools. This keynote examines the lithography equipment roadmaps essential to sustaining the AI revolution.

Junya Matsunami, PhD, is device technology expert at Technology Development Center of ASML, where he has led research into customer roadmap and patterning requirements for 3D NAND and next-generation memories since 2021. Prior to joining ASML, he spent over a decade (2008–2021) at Kioxia (formerly Toshiba), where he was instrumental in developing memory cells for 2D/3D NAND and next-generation memories including PCM and CBRAM. Dr. Matsunami earned his BS and PhD in Physics from the University of Tokyo in 2003 and 2008, respectively. He served as a visiting scholar at Stanford University from 2014 to 2015.

Japan’s semiconductor industry is entering a new era defined not only by advanced manufacturing investment, but by increasing system complexity across materials, devices, packaging, manufacturing, and AI infrastructure. As the industry transitions from isolated component optimization toward highly interconnected systems, traditional approaches to semiconductor development and manufacturing are becoming insufficient.
At the same time, the rise of advanced packaging, chiplets, heterogeneous integration, and AI factories is shifting industry value toward areas where Japan has historically demonstrated global leadership: precision manufacturing, materials science, reliability engineering, and ecosystem coordination.
This keynote explores how System Technology Co-Optimization (STCO), virtual twins, Model-Based Systems Engineering (MBSE), and reference architectures are emerging as foundational capabilities for next-generation semiconductor manufacturing. Beginning with workforce development and knowledge creation, the presentation follows the semiconductor value chain from materials and process technologies to devices, advanced packaging, industrial systems, and AI factories.
The session will discuss how connected virtual environments can enable greater collaboration across semiconductor ecosystems while improving manufacturability, reliability, lifecycle traceability, and deployment speed. Particular focus will be placed on the growing importance of system-level orchestration and the convergence of semiconductor engineering with automotive, robotics, industrial infrastructure, and AI computing systems.
The presentation will also examine how Japan’s historic strengths in monozukuri, precision manufacturing, and industrial systems integration uniquely position the country to lead the next phase of semiconductor innovation in the AI era.

John Maculley is Director of Global High-Tech Industry Business Consulting at Dassault Systèmes, with more than 20 years of experience driving innovation across the semiconductor and electronics industries. Based in Silicon Valley, he collaborates with leading foundries, OSATs, design houses, and research institutes to advance system technology co-optimization (STCO), AI infrastructure, and advanced semiconductor packaging.

John leads initiatives applying model-based systems engineering (MBSE) and virtual twins to AI Factories, including collaboration with NVIDIA on AI Factory Reference Architectures designed to accelerate deployment and reduce time-to-first-token (TT1T). His work also focuses on high-bandwidth memory (HBM) multi-physics simulation and AI-enabled collective intelligence through Industry World Models, Generative Engineering, and Virtual Companions.

Previously, John held senior leadership roles at Micron Technology and earlier worked at NASA, GE Aerospace, and Boeing. He is a frequent keynote speaker at major industry events and holds an MBA from William & Mary and a BS from San Diego State University.