Semiconductor is a key technology for digitalization, decarbonization, and economic security. The pandemic has accelerated digitization, increasing the demand for high-performance, low-power semiconductors, especially with AI advancements like ChatGPT. To meet this demand, new production technologies, such as 2.5D/3D and chiplet packaging, are essential. In June 2021, Japan’s Ministry of Economy, Trade and Industry launched the “Semiconductor and Digital Industry Strategy,” revising it in June 2023. In this article, we will introduce the latest trends in semiconductor policy, including the above-mentioned advanced packaging technology and other production and manufacturing technologies.

He joined METI in 2006. He holds a master’s degree in public policy from the University of California, Berkeley. Since 2017, he has served as Secretary to the Special Advisor to the Prime Minister, Deputy Director of Economic Partnership Division in Trade Policy Bureau, Special Assistant to Director-General in Policy Planning and Coordination Division of Industrial Science and Technology Policy and Environment Bureau, Special Assistant to Director-General in Policy Planning and Coordination Division of Minister’s Secretariat, before assuming his current position in July 2023.

Since the introduction of Generative AI, various possibilities and challenges are emerging. In this talk, I will discuss how semiconductor manufacturing can be advanced using LLM and AI-supported simulations. Also what kind of semiconductors are required and challenged for realizing AI in the future.

Aiming to revive Japan’s semiconductor technology, we are currently working with our partners to develop a manufacturing technology for cutting-edge 2nm-node semiconductors at our development center in Albany, New York to be produced at a Japanese government-led factory. In order for 2nm-node LSI’s to be internationally competitive, it is necessary to achieve volume production yields, while at the same time introducing technology to reduce the RC (resistance x capacitance) of interconnects, which significantly reduces circuit performance and increases power consumption. Furthermore, at the 1.4nm node and beyond, the life of Cu interconnects is finally approaching its limit, and research and development is underway on alternative interconnect technologies such as subtractive Ru interconnects to replace Cu, intermetallic compounds, and 2D conductors. In this report, after summarizing the technological innovations that interconnect technology has undergone in response to down scaling over the past 20 years, then discuss new technologies required for the 2nm node, and finally introduce research and development on alternative interconnect technologies for the 1.4nm node and beyond.

Takeshi Nogami is Principal Research Staff Member of IBM Research working on advanced interconnect technologies in Albany, NY, USA since 2006. He is also Visiting Professor of University of Tsukuba, Japan. He developed CuMn alloy interconnect technology and CVD-Co liner technology for Cu extension. Currently his major focuses are on development of2 nm node interconnect technology and exploratory research work toward 1.4 nm node Cu extension node and innovative alternative conductors. Prior to IBM, he worked for Toshiba, Kawasaki Steel, AMD and Sony corporation. He received BE, ME and Ph.D. from University of Tokyo. He is IEEE Senior Member. He owns over 250 US patents.

In May 2019, NTT announced the Innovative Optical and Wireless Network (IOWN), a next-generation telecommunications infrastructure initiative. To realize the concept of IOWN, an information processing infrastructure characterized by high capacity, ultra-high speed, and ultra-low latency with greatly reduced power consumption, the key technologies to be developed and pioneered are “All photonics Network (APN)” and “Photonics-Electronics Convergence (PEC)”, which combines optical and electrical technologies with silicon integrated circuits that underpin modern electronics. In addition, NTT formulated a new environment and energy vision “NTT Green Innovation Toward 2040” to simultaneously achieve zero environmental impact and economic growth by “Reduction of Environmental Impact through Business Activities” and “Creation of Breakthrough Innovation” in 2021.
NTT Basic Research Laboratories (NTT-BRL) has contributed to driving these visions by continuously challenging itself to expand scientific knowledge, create technological breakthroughs, and pioneer the next grand challenges, which transcend the barriers of conventional technologies from the viewpoints of capacity, speed, energy, size, precision, security and so on. In this talk, I will introduce NTT-BRL’s recent activities on Si-photonics-based PEC devices for optical data processing acceleration, ultrawide-gap semiconductors that are one of the advanced semiconductors contributing to Green Transformation, and PHz-wave technology that enables expanding the current limit of optical technology in APN, which will advance the concept of IOWN and open the door to a further future beyond it.

Katsuya Oguri
Vice President, Head of NTT Basic Research Laboratories and Executive Senior Research Scientist, Director of Advanced Applied Physical Science Laboratory in Nippon Telegraph and Telephone Corporation, He received a B.S., M.S., and Ph.D. from the University of Tokyo in 1996, 1998, and 2005. In 1998, he joined NTT Basic Research Laboratories. He has been a guest researcher at RIKEN since 2015 and an associate professor at University of Tsukuba Graduate School Cooperative Graduate School System since 2020. He received the 26th Japan Society of Applied Physics Japanese Journal of Applied Physics (JJAP) Best Original Paper Award in 2004 and the 18th Japan Society of Applied Physics JJAP Young Scientist Presentation Award in 2005. He received the 32nd Laser Society of Japan Best Original Paper Award in 2008. He received the Best Poster Presenter Award at International Symposium on Ultrafast Intense Laser Science XVI in 2017. He is a member of the Japan Society of Applied Physics (JSAP), the Physical Society of Japan (JPS), the Laser Society of Japan (LSJ), the Japan Intense Light Field Science Society (JILS), and Optica. He is a committee member of the Ultrafast Optoelectronics Technical Group in the Institute of Electronics, Information and Communication Engineers (IEICE).

In situations where massive amounts of data are generated, such as in training AI and automotive AI for autonomous driving, the AI hardware module functions are required to achieve both high energy efficiency and low-latency real-time processing. Chiplet can enable these requirements. To realize chiplet, it is necessary to equip the package substrate or RDL interposer with the global wiring functions of traditional monolithic chips. Furthermore, to achieve high-speed transmission specifications, polymer RDL interposers with low Dk and low Df polymer dielectric film, replacing the conventional SiO2, are required. Currently, fine wiring technology formed with polymer RDL primarily utilizes photosensitivity. As a result, via formation presents more challenges in miniaturization compared to line and space. Therefore, we attempted to form polymer vias by introducing semiconductor fine processing methods using plasma dry etching technology. This presentation introduces the latest developments in plasma dry etching for three types of films: polyimide, ABF, and m-PPE. Additionally, we propose etching technology for deep through dielectric vias (TDV) in preparation for the future stacking of chiplets, akin to multilayer wiring, known as quasi-monolithic chips (QMC).

Yasuhiro joined ULVAC in 1997. He earned his Master in Electrical engineering from the University of Toyo in 1997. And, he received a Dr. in Material Engineering from the University of Tokyo in 2003. He is currently working as a manager of institute of advanced technology at ULVAC in Shizuoka, Japan. His main interests are development of plasma technologies and equipment for the advanced packaging of integrate of semiconductor chip. He is a member of the Japan Society of Applied Physics and the Japan Institute of Electronics Packaging.
And, program committee of international symposium on dry process (DPS), and chair of technical program committee of international conference on electronics packaging (ICEP).