I will present recent trends in advanced packaging technologies (2D, 2.5D, 3.5D, CPO) and explain our research results (thermal management, hybrid bonding, etc.)

I received a Ph.D. in Engineering from Tohoku University
At Bosch, I was involved in the development of physical sensors using semiconductor technology. I then moved to Waseda University, where I conducted research and development on core semiconductor technologies (surface treatment, bonding) and physical sensors. Currently, at National Cheng Kung University, I am engaged in research and development on heterogeneous integration, focusing primarily on semiconductor back-end processes. I am collaborating on joint research projects with nine Japanese companies, three Taiwanese companies, and four universities.

The rapid evolution of AI demands a paradigm shift in semiconductor performance, specifically in compute density and memory bandwidth. To meet these requirements, the industry is aggressively scaling logic and memory while pivoting toward heterogeneous integration. These architectural shifts impose a new frontier of technical requirements on lithography tools. This keynote examines the lithography equipment roadmaps essential to sustaining the AI revolution.

Junya Matsunami, PhD, is device technology expert at Technology Development Center of ASML, where he has led research into customer roadmap and patterning requirements for 3D NAND and next-generation memories since 2021. Prior to joining ASML, he spent over a decade (2008–2021) at Kioxia (formerly Toshiba), where he was instrumental in developing memory cells for 2D/3D NAND and next-generation memories including PCM and CBRAM. Dr. Matsunami earned his BS and PhD in Physics from the University of Tokyo in 2003 and 2008, respectively. He served as a visiting scholar at Stanford University from 2014 to 2015.

Japan’s semiconductor industry is entering a new era defined not only by advanced manufacturing investment, but by increasing system complexity across materials, devices, packaging, manufacturing, and AI infrastructure. As the industry transitions from isolated component optimization toward highly interconnected systems, traditional approaches to semiconductor development and manufacturing are becoming insufficient.
At the same time, the rise of advanced packaging, chiplets, heterogeneous integration, and AI factories is shifting industry value toward areas where Japan has historically demonstrated global leadership: precision manufacturing, materials science, reliability engineering, and ecosystem coordination.
This keynote explores how System Technology Co-Optimization (STCO), virtual twins, Model-Based Systems Engineering (MBSE), and reference architectures are emerging as foundational capabilities for next-generation semiconductor manufacturing. Beginning with workforce development and knowledge creation, the presentation follows the semiconductor value chain from materials and process technologies to devices, advanced packaging, industrial systems, and AI factories.
The session will discuss how connected virtual environments can enable greater collaboration across semiconductor ecosystems while improving manufacturability, reliability, lifecycle traceability, and deployment speed. Particular focus will be placed on the growing importance of system-level orchestration and the convergence of semiconductor engineering with automotive, robotics, industrial infrastructure, and AI computing systems.
The presentation will also examine how Japan’s historic strengths in monozukuri, precision manufacturing, and industrial systems integration uniquely position the country to lead the next phase of semiconductor innovation in the AI era.

John Maculley is Director of Global High-Tech Industry Business Consulting at Dassault Systèmes, with more than 20 years of experience driving innovation across the semiconductor and electronics industries. Based in Silicon Valley, he collaborates with leading foundries, OSATs, design houses, and research institutes to advance system technology co-optimization (STCO), AI infrastructure, and advanced semiconductor packaging.

John leads initiatives applying model-based systems engineering (MBSE) and virtual twins to AI Factories, including collaboration with NVIDIA on AI Factory Reference Architectures designed to accelerate deployment and reduce time-to-first-token (TT1T). His work also focuses on high-bandwidth memory (HBM) multi-physics simulation and AI-enabled collective intelligence through Industry World Models, Generative Engineering, and Virtual Companions.

Previously, John held senior leadership roles at Micron Technology and earlier worked at NASA, GE Aerospace, and Boeing. He is a frequent keynote speaker at major industry events and holds an MBA from William & Mary and a BS from San Diego State University.

TBA

Steven Scheer was appointed Senior Vice President of compute technologies & systems / compute system scaling in 2024. In this role, he is responsible for driving sustainable advancements in functional and system scaling, with a focus on logic, memory, 3D integration, and advanced patterning. Steven joined imec in 2019, where he led the Advanced Patterning, Process, and Materials (APPM) organization. His work there encompassed patterning, unit process, and new materials development for logic, memory, photonics, and 3D integration.
Before joining imec, Steven was Account Technology Director with Tokyo Electron Ltd. (TEL), overseeing customer accounts in the Portland, OR area. During his 13-year tenure at TEL, he was responsible for R&D in patterning and cleaning technologies, holding management roles in the US, at TEL’s factory in Kumamoto, Japan, and within the corporate R&D organization in Tokyo. Steven began his research career at IBM in Fishkill, NY, working on 90 nm and 65 nm patterning development.
He holds a Ph.D. in Chemical Engineering from the University of Texas at Austin.

As the semiconductor industry advances beyond the 2nm node, market competitiveness is no longer defined solely by lithographic scaling, but by the diversification of integration technologies and system-level optimization. This keynote addresses a critical paradigm shift: moving away from FEOL/BEOL-centric scaling toward a holistic optimization framework centered on the middle-of-line (MOL), driven by its convergence with packaging technologies. The talk will review key scaling enablers underpinning EUV lithography alongside recent advances in multi-patterning. Furthermore, it highlights advanced packaging approaches—such as 3D stacking and heterogeneous integration within chiplet architectures—as the bedrock for next-generation systems. In addition to exploring quantitative cost modeling based on SEMI standards, we will discuss alignment scaling challenges in 3D integration extending to panel-level packaging (PLP). Finally, the talk evaluates the profitability of these emerging technologies from a cost-of-capital perspective, emphasizing how large-scale semiconductor investments must balance technological leaps with capital efficiency. This keynote contends that future value creation lies in cross-domain, system-driven innovation rather than geometric scaling alone.

Dr. Kazuya Okamoto is a Professor at the Graduate School of Management of Technology, Nippon Institute of Technology, and concurrently serves as a Guest Professor at the Institute for NanoScience Design, The University of Osaka. He began his career in industry, engaging in CMOS R&D and contributing to strategic business development for advanced manufacturing and inspection systems, with a focus on state-of-the-art lithography platforms and precision wafer bonding for 3D integration. He later transitioned to academia, serving as a Professor at Yamaguchi University, a national university in Japan, prior to his current appointment in 2023. Dr. Okamoto has held several high-profile leadership roles, including Chair of the JSPS R&D Committee, and currently serves as an expert committee member for a Cabinet Office program. His current research explores value creation in advanced semiconductors through rigorous industry analysis grounded in intellectual property insights, drawing on his expertise in semiconductor manufacturing systems, systems engineering, and integrated optics. He holds a Ph.D. in Electronic Engineering from the University of Tokyo.

Artificial intelligence is entering a new era, evolving into agentic systems capable of reasoning and executing complex workflows. At the same time, semiconductor design and manufacturing are at a critical inflection point, driven by AI demand and system complexity.
Cadence addresses this transformation through its “AI for Design” and “Design for AI” strategy, combining AI agents, principled simulation and optimization, and cloud-scale compute and data.
In this session, we introduce Cadence AI Super Agents and AgentStack, enabling end-to-end workflow orchestration, while highlighting the expansion of AI into physics-based and multiphysics domains.

Graduated from the Faculty of Informatics, University of Wollongong.
After working for a Japanese semiconductor trading company, joined Cadence Design Systems in 2001.
At Cadence, he served as leader of the Digital Implementation and Signoff Analysis Groups,
driving technological innovation and customer projects in the implementation
and signoff areas of advanced semiconductor design.
Subsequently, he became the overall head of the Application Engineering (AE) team at Cadence Japan,
leading the strengthening and advancement of technical support systems for domestic customers.
Currently, he is working to transform semiconductor design
and manufacturing through the promotion of AI-powered design methodologies and cloud-based design environments,
contributing to the advancement of EDA technology and the creation of customer value.